Along with increase in a traffic volume of the Internet, it has been required to improve a transmission speed of a SerDes used for an information processing device such as an optical module, router/server, and a RAID. Meanwhile, as seen in Green IT, reduction in a power consumption of the information device has been advanced, and reduction in the power consumption of the SerDes has also been required.
Conventionally, as the SerDes, there has been a technique disclosed in, for example, “Equalizer Implementation for 10 Gbps Serial Data Link in 90 nm CMOS Technology.”, IEEE ICM-December 2007, written by Ahmed Abd El-Fattah (Non-Patent Document 1).
Here, an example of a conventional SerDes will be described with reference to FIGS. 9 to 11. FIG. 9 is a configuration diagram illustrating an example of the conventional SerDes, FIG. 10 is a configuration diagram illustrating an example of a conventional receiver, and FIG. 11 is a circuit diagram illustrating a configuration of a conventional variable gain circuit.
In FIG. 9, the SerDes is composed of: a sending unit 704 composed of a driver 701 and a parallel/serial converting circuit 702; and a receiving unit 705 composed of a receiver 208 including a variable gain circuit 201 and a serial/parallel converting circuit 703.
In FIG. 10, the receiver 208 is composed of: the variable gain circuit 201; an equalizer circuit 202; a limit amplifier 203; input terminals 204 and 205; and output terminals 206 and 207. The variable gain circuit 201 matches an input resistance of the receiver with a characteristic impedance of a substrate wiring to suppress reflection noises and equalizes variations in an input signal amplitude due to a difference in a wiring length.
A high-frequency property and power consumption of the receiving device are influenced by the variable gain circuit.
In FIG. 11, the conventional variable gain circuit 201 has a configuration in which, resistors 1001 and 1002 and output terminals 1008 and 1009 are connected to drains, current sources 1007 and 1006 are connected to sources, and a variable resistor 1005 is inserted between sources of transistors 1003 and 1004, and a gain is varied by changing a resistance value of the variable resistor 1005. Moreover, terminating resistors 1012 and 1013 are connected to input terminals 1010 and 1011, respectively, to be matched with the characteristic impedance of the substrate wiring.